Characterization of Single Event Upsets in 32 nm SOI Technology using Alpha Particle and Heavy-ion Radiation Sources

Abstract

The response of electronic devices to ionizing radiation is a reliability concern for commercial and space applications. An ionizing particle can cause charge to be generated and collected at the node of a circuit. If the charge is collected in the memory element, a single event upset (SEU) can occur. Since the discovery of single event effects, circuit designers have faced the challenge of creating radiation hardened by design (RHBD) flip-flops that decrease the memory element’s susceptibility to SEUs. Test structures of unhardened and hardened flip-flop designs are fabricated and irradiated in order to understand the relative error rates due to single event upsets. Each test structure is irradiated using heavy-ion particle accelerators to simulate the radiation in a space environment. In the past only particles with a relatively high linear energy transfer (LET) were capable of generating enough charge to flip the state of a memory element. However, as technology has scaled, the critical charge necessary to cause an SEU has decreased. Radiation effects must now be considered in calculating the error rate for commercial applications as well. Irradiating circuits using isotropic button sources simulates terrestrial radiation such as alpha particles emitted from packaging material. The continued improvement of RHBD techniques relies on the ability to thoroughly test circuits at each new technology node over all radiation environments and understand how the cells upset.

In this thesis, SEU data for hardened and unhardened flip-flop designs from a variety of radiation sources are presented. The combination of data from heavy-ion beam, alpha particle beam, and isotropic alpha particle sources provides the critical parameters for calculating error rate for a given flip-flop design in a specific environment. Heavy-ion data also reveals the robust design of DICE, DICE Guard Gate, and Stacked flip-flops in comparison with unhardened flip-flop designs in 32 nm SOI technology.