A Built-In Self-Test (BIST) Technique for Single-Event Transient Testing in Digital Circuits

Abstract

With shrinking device feature sizes, integrated circuits are becoming more vulnerable to Single-Event Transients (SETs). Characterizing error rates due to SETs is essential for choosing appropriate hardening techniques to assure a digital circuit’s radiation tolerance. However, single-event testing may be expensive, complicated and time consuming. This thesis has illustrated how built-in self-testing alternatives can be used to estimate the radiation response of a circuit without costly equipment and test facilities. The BIST, by electrically injecting pulses of randomly varying width and arrival times with respect to the clock, mimic the actual SET unpredictability. Simulation and experimental results from the 180 nm technology node show that pulses in the range of 300 ps to about 5 ns can be generated. With the use of equivalent-inputs, the number of nodes for BIST testing may be reduced by orders of magnitude below the actual node count of the circuit. In the case of the 16-bit adder and 4-bit multiplier, about 80% of the total soft errors can be accounted for by testing only 5% of the nodes in the circuit. These results demonstrate the feasibility of the BIST technique for testing complex ICs intended for radiation environments in a very cost-effective manner. The area penalty for implementing a BIST circuit will vary according to the application, but will be minimal for larger circuits. In a nutshell, BIST is a cost effective method of testing for SETs in any conventional laboratory that can give an overall estimate of the circuit’s vulnerability to single-events.