TECHNIQUES TO MITIGATE DIGITAL BIT CORRUPTION IN SILICON-ON-INSULATOR FLASH ANALOG-TO-DIGITAL CONVERTERS

Abstract

This work provides a high-speed flash-analog-to-digital converter with an increased resistance to ionizing radiation, specialized for use in sub-50 nm Silicon-On-Insulator technology nodes. When applying Radiation Hardened by Design methods to increase circuit resistance to ionizing radiation design penalties are incurred on circuit performance. This work seeks to minimize these design penalties while maintaining radiation hardness by applying a novel Most Significant Bit circuit protection and correction technique. Circuit design and verification has been done using sub-50 nm nodes within the Cadence Virtuoso environment and data verified single event simulations have been applied to develop radiation hardening methods. This circuit targeting only the most significant radiation induced errors has been shown to provide radiation hardness while minimizing design penalties due to additional circuitry.