Layout-Aware Modeling and Analysis Methodologies for Transient Radiation Effects on Integrated Circuit Electronics

Abstract

The development of integrated circuits intended for use in transient radiation environments must account for the impact of the environment on the operation of the circuit. The design of integrated circuits is increasingly simulation driven, and increased costs to fabricate designs require engineers to consider radiation effects in the simulation and design phase to limit fabrication and test cycles required to produce a radiation hardened part. This work advances the historical modeling approaches with bias-dependent and layout-aware methods for modeling the dose-rate and single-event effects in advanced technologies.

This research develops a bias-dependent modeling method that accounts for circuit induced shaping of the device-level transient current. Behavioral modeling languages are utilized to eliminate independent current sources and lumped SPICE element models. Dose rate models are developed for multiple dielectrically-isolated processes across technology types, accounting for real-time bias-dependence and layout geometries in modern integrated circuit processes. Single-event modeling methods are developed to capture the bias-dependent current response observed in recent TCAD simulations. Bulk CMOS and SiGe HBT technology model parameterization for multiple-device charge collection is demonstrated. A new geometry-aware single-event model for sub-50nm partially-depleted SOI CMOS with an integrated parasitic BJT parameterized by technology and design parameters is developed. Dose-rate and single-event model simulations compare well to TCAD and test data.

A novel layout-aware analysis method is developed, utilizing a hybrid of compact models (for efficiency) and spatially-aware layout objects (for geometric charge collection accuracy), in an industry standard integrated circuit design tool flow. The layout-aware analysis provides designers with visual feedback about the sensitivity of a design directly referenced to the circuit layout.

The methods developed in this research are being actively utilized in radiation-effects research at universities, aerospace and defense corporations, and commercial integrated circuit design and manufacturing facilities. Layout-aware radiation-enabled models using the methodologies developed in this work have been integrated with process design kits and deployed to the radiation-hardened-by-design community. This research develops capabilities that provide a path forward to model transient radiation effects in advanced integrated circuit technologies.