An analysis of error detection techniques for arithmetic logic units

Abstract

Scaling in VLSI systems leads to higher packing densities for transistors. As a result, they are more likely to be hit by an incident particle, such as neutrons or alpha particles. The interaction of neutron and alpha particles with semiconductor devices may lead to permanent, intermittent, or transient faults that result in an error. Thus, error detection becomes a greater concern for system reliability as transistor size decreases. To achieve the desired reliability, computer architects investigate new techniques to detect and correct soft errors caused by transient faults. Usually, a tradeoff is made between the performance of a processor and the area and power required for error detection. This thesis uses a 45-nm cell library to synthesize hardware description language (HDL) models for selected error detection techniques when used with Arithmetic Logic Units (ALUs). Key results include a drastic increase in power consumption for some techniques as the bit-width of the ALU increases. Results are also compared to the baseline of dual modular redundancy (DMR).