Analysis of single event transients in dynamic logic circuitry

Abstract

Dynamic logic circuitry is generally faster and smaller than equivalent static logic circuits. The use of these circuits in space is desirable, but not much work has been performed in assessing their vulnerability to the ionizing particles present in the space environment. These particles can generate transient currents that can affect circuit performance. The effects of single event transients on dynamic logic circuitry are studied. Simulations are performed using the IBM 130nm and 90nm processes. Mechanisms of upset are determined for both precharge and evaluate phases of dynamic logic. Frequency effects, stage length dependency, keeper effects, and LET effects are all considered. An analysis by hit nodes on a dynamic full adder circuit is performed at varying frequencies. Results are compared with equivalent static logic circuits.