Analysis of single event vulnerabilities in a 130 nm CMOS technology

Abstract

The amount of charge required to represent a logic state in CMOS digital circuits has been reduced dramatically with the scaling of supply voltage and nodal capacitances, making radiation-induced single event effects increasingly problematic. Circuit hardening approaches, such as Triple Mode Redundancy (TMR) and Dual Interlocked Storage Cell (DICE latch) have been employed to address this issue; however many of these techniques are designed to mitigate effects of charge deposited at a single circuit node. Decreased spacing of devices with scaling can increase the charge collection at nodes other that than the hit node. Such charge collection at multiple nodes due to a single hit (i.e. “charge sharing”) can render existing methods for Single Event Upset (SEU) mitigation ineffective. Using three-dimensional (3D) device-level TCAD simulations, the mechanisms responsible for charge sharing were determined for the 130 nm technology node. Parasitic bipolar turn-on is shown to be the primary mechanism for charge sharing between two PMOS transistors, whereas charge diffusion is the primary mechanism responsible for charge sharing in NMOS transistors. Mitigation techniques explored showed that the use of a contacted guard-band reduced the charge sharing between PMOS devices in the n-well by 97% and between NMOS devices in the p-well by 35%. A combination of circuit simulations, 3D TCAD simulations, and mixed-mode simulations show that charge sharing between sensitive pairs of devices is the primary reason for experimentally observed upsets in the DICE latch design when exposed to low LET ions. The use of contacted guard-band, interdigitation, and nodal separation of sensitive nodes on the layout level can be employed to retain the hardness of the DICE latch and other circuit level hardening techniques.