| dc.description.abstract | An estimated 50% of the electricity in the world is controlled by power semiconductor devices, with silicon carbide power devices superior to silicon power devices due to higher breakdown electric fields, increased thermal conductivity and significantly lower on-state resistance, all of which result in size, weight, and power (SWaP), and overall cost savings, making them ideal candidates for space-based applications. However, microelectronic devices and circuits used in space may be susceptible to naturally occurring radiation, such as heavy ions. Obtaining radiation data for semi- conductor devices is an expensive, time-consuming task with single event burnout (SEB) testing particularly challenging because the destructive nature results in de- vices that are no longer functional. The safe operating area (SOA) for 1200 V SiC power MOSFETs and diodes has been modestly characterized through test campaigns, however, little insight has been gained for the physical mechanism(s) that may be responsible for ion-induced single event burnout. Understanding these mechanisms is imperative for organizations making space-flight hardware design decisions
to mitigate risk of operational failure during a mission.
In this dissertation, matching single event burnout thresholds for SiC MOSFETs
and diodes are identified, suggesting a common mechanism for failure, which is unique because silicon power MOSFETs and diodes have differing mechanisms responsible for failure. 3D TCAD simulations provide physical insight into the ion-induced response of both MOSFETS and diodes, and analysis establishes that ion-induced, highly- localized energy pulses are the mechanism responsible for single event burnout in SiC. Finally, single event burnout date trends are analyzed for devices with increased rated breakdown voltage, and the trends are explained using 3D TCAD simulations. A trade-space analysis for the device variants provides a demonstration for selecting the device with a higher single event burnout tolerance while minimizing performance losses. | |
