Analysis and hardening of all-digital phase-locked loops (ADPLLs) to single-event radiation effects

Abstract

In deep sub-micron CMOS technologies, all-digital phase-locked loops (ADPLLs) are favored over conventional analog or mixed-signal phase-locked loops (A/MS) PLLs for providing the clock signals for modern integrated circuits (ICs). Since an accurate clock signal is an important guarantee of the correct functionality of a system on chip (SOC), single-event effects (SEEs), as a type of reliability issues, have been extensively studied in A/MS PLLs, which are mostly based on a charge-pump PLL (CPPLL) architecture. However, little is known about the single-event vulnerability and hardening of ADPLLs. In this dissertation, three major single-event error signatures were identified and perturbation time error metric was proposed to quantify the error signatures in ADPLLs. Circuit-level simulation and experimental testing were conducted to characterize the subcircuits of different types ADPLLs to distinguish and analyze their individual contribution to the overall ADPLL SE vulnerability. High-order pole registers in the DLF were identified to be the most sensitive module in ADPLLs. In addition, different ADPLLs with complex system architectures were also characterized and analyzed for SE vulnerability. Additionally, a novel time-domain model for SEU-induced errors in ADPLLs was proposed and verified with experimental results. The model successfully predicts the output time-domain response and perturbation time of the ADPLLs for any SEUs in any sub-circuits, which allows designers to distinguish the most SE sensitive modules in the ADPLL topology and apply selective hardening solutions before tapeout. RHBD hardening guidelines for different types of ADPLLs for different operating environment and targeted design specifications were proposed based on SE characterization and modeling of the ADPLL designs. Last but not least, the proposed model and hardening techniques are compared with existing work on A/MS PLLs to provide conventional PLL designers with insights on RHBD ADPLL designs.